1. Field of the Invention
The invention relates to an EEPROM process, and more particularly to a method to increase wordline density by reducing wordline widths of and space therebetween.
2. Description of the Related Art
Digital information is stored in a memory cell wherein the memory cell acts as a single digital bit. Hence, a plurality of digital bits is stored in a plurality of memory cells. The memory cells are arranged be array, and each memory cell is set at predetermined address by column and row. The memory cells in the same column or row are strung together with the same conducting wire which is called a wordline.
FIGS. 1a to 1b are cross-sections of the conventional method for forming wordlines of an EEPROM.
In FIG. 1a, a semiconductor substrate 101 is provided, and a plurality of memory cells and other elements can be formed thereon. A poly layer 102, a WSi layer 103, a patterned photoresist layer 104 with an opening 105 are sequentially formed in the semiconductor substrate 101. The width of the opening 105 is 0.18 μm, and a portion of the surface of the WSi layer 103 is exposed by the opening 105.
In FIG. 1b, the WSi layer 103 and the poly layer 102 are anisotropically etched using the patterned photoresist layer 104 as an etching mask until the semiconductor substrate 101 is exposed to form an opening 106. After the photoresist layer 104 is removed, wordlines 107a and 107b are formed and separated by the opening 106. The widths of the wordlines 107a and 107b are both 0.14 μm. The size of the opening 106 matches the size of the opening 105 of the patterned photoresist layer 104.
Due to the restrictions of the characteristics of the light source and the photoresist layer, an insufficiently thick photoresist layer with cannot effectively isolate the etching source. Conversely, when an excessively thick photoresist layer is used, the size of the contact window is difficult to control. Possible collapse of the photoresist layer should also be prevented.